ELECTRONICS II

DIGITAL ELECTRONICSnextuppreviouscontents

CONTENT

Problems

7. Digital Circuits

Analog signals have a continuous range of values within some specified limits and can be associated with continuous physical phenomena.

Digital signals typically assume only two discrete values (states) and are appropriate for any phenomena involving counting or integer numbers.

While we were mostly interested in voltages and currents at specific points in analog circuits, we will be interested in the information flow in digital circuits.

The active elements in digital circuits are either bipolar transistors or FETs. These transistors are permitted to operate in only two states, which normally correspond to two output voltages. Hence the transistors act as switches.

Before starting we will first review number systems and Boolean algebra.

 

 

 

Number Systems

The two digital states can be given various names: ON/OFF, true/false, high/low, 1/0, etc.. The 1 and 0 notation naturally leads to the use of binary (base 2) numbers. Octal (base 8) and hexadecimal (base 16) numbers are also used since they provide a condensed number notation. Decimal (base 10) numbers are not of much use in digital electronics.

 

 

Binary, Octal and Hexadecimal Numbers

Consider a decimal number with digits a b c. We can write abc as

Similarly, in the binary system a number with digits a b c can be written as

Each digit is known as a bit and can take on only two values: 0 or 1. The left most bit is the highest-order bit and represents the most significant bit (MSB), while the lowest-order bit is the least significant bit (LSB).

Conversion from binary to decimal can be done using a set of rules, but it is much easier to use a calculator or tables (table 7.1).

 
Table 7.1:  Decimal, binary, hexadecimal and octal equivalents.

The eight octal numbers are represented with the symbols , while the 16 hexadecimal numbers use .

In the octal system a number with digits a b c can be written as

while one in the hexadecimal system is written as

A binary number is converted to octal by grouping the bits in groups of three, and converted to hexadecimal by grouping the bits in groups of four. Octal to hexadecimal conversion, or visa versa, is most easily performed by first converting to binary.

Example: Convert the binary number 1001 1110 to hexadecimal and to decimal.

Example: Convert the octal number to hexadecimal.

Example: Convert the number 146 to binary by repeated subtraction of the largest power of 2 contained in the remaining number.

Example: Devise a method similar to that used in the previous problem and convert 785 to hexadecimal by subtracting powers of 16.

 

Number Representation

We define the following

word: a binary number consisting of an arbitrary number of bits.

nibble: a 4-bit word (one hexadecimal digit).

byte: an 8-bit word.

We often use the expressions 16-bit word (short word) or 32-bit word (long word) depending on the type of computer being used. Most fast computers today actually employ a 64-bit word at the hardware level.

If a word has n bits it can represent different numbers in the range 0 to . Negative numbers are usually represented by the so called 2's complement notation. To obtain the 2's compliment of a number first take the complement (invert each bit) and then add 1. All the negative numbers will have a 1 in the MSB position, and the numbers will now range from to . The electronic advantages of the 2's complement notation becomes evident when addition is performed. Convince yourself of this advantage.

 

Boolean Algebra

The binary 0 and 1 states are naturally related to the true and false logic variables. We will find the following Boolean algebra useful. Consider two logic variables A and B and the result of some Boolean logic operation Q. We can define

Q is true if and only if A is true AND B is true.

Q is true if A is true OR B is true.

Q is true if A is false.

A useful way of displaying the results of a Boolean operation is with a truth table. We will make extensive use of truth tables later. If no ``-'' is available on your text processor or circuit drawing program an ``N'' can be used, ie. .

We list a few trivial Boolean rules in table 7.2.

 
Table 7.2:  Properties of Boolean Operations.

The Boolean operations obey the usual commutative, distributive and associative rules of normal algebra (table 7.3).

 
Table 7.3:  Boolean commutative, distributive and associative rules.

We will also make extensive use of De Morgan's theorems (table 7.4).

 
Table 7.4:  De Morgan's theorems.

 

Logic Gates

Electronic circuits which combine digital signals according to the Boolean algebra are referred to as logic gates; gates because they control the flow of information. Positive logic is an electronic representation in which the true state is at a higher voltage, while negative logic has the true state at a lower voltage. We will use the positive logic type in this course.

In digital circuits all inputs must be connected.

Logic circuits are grouped into families, each with their own set of detailed operating rules. Some common logic families are:

RTL: resistor-transistor logic,

DTL: diode-transistor logic,

TTL: transistor-transistor logic,

NMOS: N-channel metal-oxide silicon,

CMOS: complementary metal-oxide silicon and

ECL: emitter-coupled logic.

The ECL is very fast. The MOS features very low power consumption and hence is often used in LSI technology. The TTL is normally used for small-scale integrated circuit units.

The schematic symbols of the basic gates and the logic truth tables are shown in figure 7.1.

 
Figure 7.1:  Symbols and truth tables for the four basic two-input gates: a) AND, b) NAND, c) OR, d) NOR and e) the inverter.

The open circle is used to indicate the NOT or negation function and can be replaced by an inverter in any circuit. A signal is negated if it passes through the circle. Any logic operation can be formed from NAND or NOR gates or a combination of both. We also commonly have gates with more than two inputs. Inverter gates can be formed by applying the same logic signal to both inputs of an NOR or NAND gate.

 

Combinational Logic

We will design some useful circuits using the basic logic gates, and use these circuits later on as building blocks for more complicated circuits.

We describe the basic AND, NAND, OR or NOR gates as being satisfied when the inputs are such that a change in any one will change the output. A satisfied AND or NOR gate has a true output, whereas a satisfied NAND or OR gate has a false output. We sometimes identify the input logic variables A, B, C, etc. with an n-bit number .

 

Combinational Logic Design Using Truth Tables

The following steps are a useful formal approach to combinational problems:

  1. Devise a truth table of the independent input variables and the resulting output quantities.
  2. Write Boolean algebra statements that describe the truth table.
  3. Reduce the Boolean algebra.
  4. Mechanize the Boolean statements using the appropriate logic gates.

Consider the truth table that defines the OR gate. Using the lines in this table that yield a true result gives.

Since Q is a two-state variable all other input state combinations must yield a false. If the truth table had more than a single output result, each such result would require a separate equation. An alternative is to write an expression for the false condition.

 

 

The AND-OR Gate

Some logic families provide a gate known as an AND-OR-INVERT or AOI gate (figure 7.2).

 
Figure 7.2:  The basic AND-OR-INVERT gate.

 

Exclusive-OR Gate

The exclusive-OR gate (EOR or XOR) is a very useful two-input gate. The schematic symbol and truth table are shown in figure 7.3.

 
Figure 7.3:  The schematic symbol for the exclusive-OR gate (EOR or XOR) and its truth table.

From the truth table

and we can draw the mechanization directly from the truth table (figure 7.4).

 
Figure 7.4:  A mechanization of the exclusive-OR directly from the truth table.

 

Timing Diagrams

Normally signals flip from one logic state to another. The time it takes the signal to move between states is the transition time , where the time is measured between 10% and 90% of the signal levels. Delays within the logic elements result in a propagation (pulse) delay , where the time is measured between 50% of the input signal and 50% of the output response. Definitions of the transition time and propagation delay are shown in figure 7.5.

 
Figure 7.5:  The transition time of the input and output signals, and the propagation delay through a gate.

 

Signal Race

Signal racing is the condition when two or more signals change almost simultaneously. The condition may cause glitches or spikes in the output signal as shown in figure 7.6. The effects of these glitches can be eliminated by using synchronous timing techniques. In synchronous timing the glitches are allowed to come and go, and the logic state changes are initiated by a timing pulse (clock pulse).

 
Figure 7.6:  a) A timing diagram for the EOR circuit. b) An expanded view of the glitch shows it to be caused by a signal race condition.

 

Half and Full Adders

From basic gates, we will develop a full adder circuit that adds two binary numbers. Consider adding two 2-bit binary numbers and . , where is the carry bit. The truth table for all combinations of and is shown in table 7.5.

 
Table 7.5:  The binary addition of two 2-bit numbers. The column.

From the truth table

The mechanization of these two equation is shown in figure 7.7.

 
Figure 7.7:  A mechanization of the half adder using an EOR and an AND gate.

This circuit is known as the half adder. It can not handle the addition of any two arbitrary numbers because it does not allow the input of a carry bit from the addition of two previous digits. A circuit that can handle these three inputs can perform the addition of any two binary numbers.

The truth table for three input variables is shown in figure 7.8.

 
Figure 7.8:  The binary addition of two 2-bit numbers. The column.

From the truth table

This is known as majority logic. And a majority detector is shown in figure 7.9

 
Figure 7.9:  A mechanization of the majority detector.

The following device (figure 7.10) is known as a full adder and is able to add three single bits of information and return the sum bit and a carry-out bit.

 
Figure 7.10:  The full adder mechanization.

The circuit shown in figure 7.11 is able to add any two numbers of any size. The inputs are and , and the output is .

 
Figure 7.11:  A circuit capable of adding two 3-bit numbers.

Example: If the input to the circuit in figure 7.12 is written as a number ABCD, write the nine numbers that will yield a true Q.

 
Figure 7.12:  A typical logic function.

 
Table 7.6: The truth table for the typical logic function example.

ABCD=(2,3,6,7,11,12,13,14,15) gives Q true.

Example: Using the 2's complement convention, the 3-bit number ABC can represent the numbers from -3 to 3 as shown in table 7.7 (ignore -4). Assuming that A, B, C and are available as inputs, the goal is to devise a circuit that will yield a 2-bit output EF that is the absolute value of the ABC number. You have available only two- and three-input AND and OR gates.

1.      Fill a truth table with the ABC and EF bits.

The truth table is shown in table 7.7.

 
Table 7.7:  Truth table with for the ABC and EF bits.

2.      Write a Boolean algebra expression for E and for F.

3.      Mechanize these expressions.

The mechanized expressions are shown in figure 7.13.

 
Figure 7.13:  Mechanization for the ABC and EF bits.

Example: Suppose that the 2-bit binary number AB must be transmitted between devices in a noisy environment. To reduce undetected errors introduced by the transmission, an extra bit P is often included to add redundancy to the information. Assume that P is set true or false as needed to make an odd number of true bits in the resulting 3-bit number ABP. When the number is received, logic circuits are required to generate an error signal E whenever the odd number of bits condition is not met.

1.      Develop a truth table of E in terms of A, B and P.

The truth table is shown in table 7.8.

 
Table 7.8:  Truth table for E in terms of A, B and P.

2.      Write a Boolean expression for E as determined directly from the truth table.

3.      Using De Morgan's theorem twice, reduce this expression to one EOR and one NEOR operation. (This is very similar to the half-adder problem.)

 
Figure 7.14: Mechanization for E.

nextuppreviouscontents
 

Multiplexers and Decoders

Multiplexers and decoders are used when many lines of information are being gated and passed from one part of a circuit to another.

Multiplexing is when multiple data signals share a common propagation path. Time multiplexing is when different signals travel along the same wire but at different times. These devices have data and address lines, and usually include an enable/disable input. When the device is disabled the output is locked into some particular state and is not effected by the inputs. Shown in figure 7.15 is a 4-line to 1-line multiplexer.

 
Figure 7.15:  4-line to 1-line multiplexer.

A decoder de-multiplexes the signals back onto several different lines. Shown in figure 7.16 is a binary-to-octal decoder (3-line to 8-line decoder).

 
Figure 7.16:  Octal decoder.

Decoders (octal decoder) can also convert a 3-bit binary number to an output on one of eight lines. Hexadecimal decoders are 4-line to 16-line devices. When the decoder is disabled the outputs will be high. A decoder would normally be disabled while the address lines were changing to avoid glitches on the output lines.

 

Schmitt Trigger

A noisy input signal to a logic gate could cause unwanted state changes near the voltage threshold. Schmitt trigger logic reduces this problem by using two voltage thresholds: a high threshold to switch the circuit during low-to-high transitions and a lower threshold to switch the circuit during high-to-low transitions. Such a trigger scheme is immune to noise as long as the peak-to-peak amplitude of the noise is less than the difference between the threshold voltages. A gate with the Schmitt trigger feature has a small hysteresis curve drawn inside the gate symbol. Schmitt triggers are mostly used in inverters or simple gates to condition slow or noisy signals before passing them to more critical parts of the logic circuit.

 

The Data Bus

A bus is a common wire connecting various points in a circuit; examples are the ground bus and power bus. The data bus carries digital information. A data bus is usually a group of parallel wires connecting different parts of a circuit with each individual wire carrying a different logic signal. The data bus is connected to the inputs of several gates and to the outputs of several gates. You cannot connect directly the outputs of normal gates. For this purpose three-state output logic is commonly used but will not be discussed here.

A data bus line may be time multiplexed to serve different functions at different times. At any time only one gate may drive information onto the bus line but several gates may receive it. In general, information may flow on the bus wires in both directions. This type of bus is referred to as a bidirectional data bus.

 

Two-State Storage Elements

Analog voltage storage times are limited since the charge on a capacitor will eventually leak away. The problem of discrete storage reduces to the need to store a large number of two-state variables. The four commonly used methods are: 1) magnetic domain orientation, 2) presence or absence of charge (not amount of charge) on a capacitor, 3) presence or absence of an electrical connection and 4) the DC current path through the latches and flip-flops of a digital circuit. We will discuss only the latter.

 

 

Latches and Un-Clocked Flip-Flops

It is possible using basic logic gates to build a circuit that remembers its present condition. It is also possible to build counting circuits. The basic counting unit is the flip-flop (FF).

 

nextuppreviouscontents
 

Latches

All latches have two inputs: data and enable/disable. And typically Q and outputs. A ones-catching latch can be built as shown in figure 7.17.

 
Figure 7.17:  An AND-OR gate used as a ``ones catching'' latch and its timing diagram.

When the control input C is false, the output Q follows the input D, but when the control input goes true, the output latches true as soon as D goes true and then stays there independent of further changes in D.

One of the most useful latches is known as the transparent latch or D-type latch. The transparent latch is like the ones-catching latch but the input D is frozen when the latch is disabled. The operation of this latch is the same as that of the statically triggered D flip-flop discussed below.

 

RS and Flip-Flops

The RS flip-flop (RSFF) is the result of cross-connecting two NOR gates as shown in figure 7.18. The RS inputs are referred to as active ones.

 
Figure 7.18:  The RS flip-flop constructed from NOR gates, and its circuit symbol and truth table.

The ideal flip-flop has only two rest states, set and reset, defined by and , respectively.

A very similar flip-flop can be constructed using two NAND gates as shown in figure 7.19. The inputs are now active zeros.

 
Figure 7.19:  The flip-flop constructed from NAND gates, and its circuit symbol and truth table.

These FFs are often referred to as the set/reset type and are un-clocked.

 

Clocked Flip-Flops

A clocked flip-flop has an additional input that allows output state changes to be synchronized to a clock pulse.

nextuppreviouscontents


Clocked RS Flip-Flop

We first consider the static clocked (level-sensitive) RS flip-flop shown in figure 7.20. The symbol x in the following tables represents either the binary state 0 or 1.

 
Figure 7.20:  The clocked RS flip-flop can be constructed from an RS flip-flop and two additional gates, the schematic symbol for the static clocked RSFF and its truth table.

The first five lines in the truth table give the static input and output states. The last four lines show the state of the outputs after a complete clock pulse p.

 

D Flip-Flop

The D flip-flop avoids the undefined states in the RSFF truth table by reducing the number of input options (figure 7.21).

 
Figure 7.21:  Statically triggered D flip-flop (transparent latch) mechanized with clocked RS, and the schematic symbol and its truth table.

The statically clocked DFF is also known as a